Active-matrix display devices display video by selecting two-dimensionally arranged display elements row by row, and writing a voltage to the selected display elements in accordance with data to be displayed. To select display elements row by row, a shift register for sequentially shifting output signals based on clock signals is used as a scanning signal line driver circuit. Also, as for display devices in which dot-sequential drive is performed, a similar shift register is provided in a data signal line driver circuit.
For some liquid crystal display devices, a production process intended to form TFTs (Thin Film Transistors) in display elements is used for forming a display element driver circuit integrally with display elements. In such a case, to reduce production cost, a driver circuit including a shift register is preferably formed using transistors of the same conductivity type as TFTs. Also, increasing the number of clock signals to be provided to the shift register results in an increased area for laying out clock wires and increased power consumption. Given such a background, the shift register is required to operate based on two-phase clock signals using transistors of the same conductivity type. When such a shift register is used in a liquid crystal display device, video disturbance caused by turning on or off the power circuit of the liquid crystal display device might be visible to the human eye, so that viewers experience a feeling of discomfort.
Therefore, if it is possible to perform all-on operation, which allows all output terminals of the shift register to output high-level output signals, when the power circuit is turned on, disturbance of video displayed on the screen can be alleviated. A known shift register capable of such all-on operation is described in Japanese Laid-Open Patent Publication No. 2002-197885.
FIG. 21 is a circuit diagram of a signal retention block included in the shift register described in Japanese Laid-Open Patent Publication No. 2002-197885. The operation of the signal retention block shown in FIG. 21 will be described. All transistors included in the signal retention block are of N-channel type. When the shift register performs all-on operation, transistors T11, T12, and T13 are brought into off state. Also, a power-supply voltage VDD is provided to a drain terminal of a diode-connected transistor T16, so that the potential of a node NB is set to high level, thereby bringing a transistor T14 into on-state. Accordingly, when an output control signal SET at a level of Va (high level) is externally provided to a control terminal CTL, the potential of a node Nout is set to (Va−Vth) (where Vth is a threshold voltage of the transistor T14). As a result, an output signal OTk at a potential level of (Va−Vth) is outputted from an output terminal OUT. In other signal retention blocks, similarly, high-level output signals are outputted simultaneously. Therefore, a shift register configured by such signal retention blocks can perform all-on operation.
[Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-197885